VDAT-2023: 27th International Symposium on VLSI Design and Test Birla Institute of Technology & Science, Pilani Pilani, India, September 29-October 1, 2023 |
Conference website | https://discovery.bits-pilani.ac.in/VDAT2023/ |
Submission link | https://easychair.org/conferences/?conf=vdat2023 |
Submission deadline | June 25, 2023 |
VLSI Design & Test Symposium (VDAT) promotes research and development in various fields of VLSI Design. VDAT began as a small workshop in the year 1998, and in 2005 it acquired the status of an international symposium. The 27th International Symposium on VLSI Design and Test (VDAT-2023) will be jointly hosted by Birla Institute of Technology & Science (BITS), Pilani, and CSIR - Central Electronics Engineering Research Institute (CSIR-CEERI), Pilani. This symposium aims to bring Industries, Academics, Researchers, Startups, MSMEs, and related practitioners together to exchange their ideas for leveraging in their respective fields. The VLSI Society of India, leading institutes and industries actively support the symposium.
Submission Guidelines
Authors are invited to submit original, unpublished research manuscripts on the above topics. Submissions must be done through the easy-chair portal: https://easychair.org/conferences/?conf=vdat2023. All papers will be peer-reviewed with a double-blind review process. Soft copies of papers should be submitted in PDF format, manuscripts should not exceed six A4 size pages, and should be uploaded online. All accepted papers must be presented by one of the authors in order to be included in the SCOPUS-indexed Springer Lecture Notes in Computer Science (LNCS) conference proceedings.
Dates & Deadlines
Regular Papers
Full Paper Submission: May 15-June 15, 2023
Notification of Acceptance: July 22, 2023
Camera Ready Paper: August 07, 2023
List of Topics
- Low-Power Integrated Circuits and Devices
- Memory, Computing & Processor Design
- VLSI Architectures and System Integration
- VLSI Testing and Security
- FPGA-based Design and Embedded Systems
- CAD for VLSI
- System-Level Design
- Emerging Integrated Circuits and Systems
Committees
General Chair
Prof. Chandra Shekhar, BITS Pilani
Prof. M Balakrishnan, IIT Delhi
Organizing Committee Chair
Dr. Nitin Chaturvedi, BITS, Pilani
Dr. Jai Gopal Pandey, CEERI, Pilani
Venue
The conference will be held in BITS, Pilani
Contact
vdat2023@pilani.bits-pilani.ac.in