The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and in 2022 the ten billionth RISC-V core was shipped, to date it has yet to gain traction in HPC.

Submission Guidelines

Online Submission System

Authors submitting papers for the RISC-V in HPC Workshop 2026 must do so via the EasyChair submission system:EasyChair submission page for RISC-V in HPC Workshop 2026.

We invite authors to submit original research papers of no more than 12 pages in PDF format, including figures and references. Papers must be formatted according to the ACM Proceedings Style and submitted through the Online Submission System.

Submitted papers must describe original work that has not appeared and is not under consideration for another conference, journal, or workshop. The review process will be double-blind, so manuscripts must be anonymized prior to submission. There will be no revision rebuttal process, and the review will be one-pass.

Submission Format

All manuscripts must be prepared in a single-column format and submitted as PDF files. Submissions should not exceed 12 pages including figures and references, and must follow the official ACM Proceedings Style.

ACM provides templates for both Word and LaTeX. Authors using LaTeX are encouraged to use the ACM template with the “manuscript” format option. Additionally, ACM has partnered with Overleaf, where the ACM LaTeX template is available.

Please follow Step 1 (Microsoft Word/LaTeX) at “2. The Workflow and Templates” in the ACM submission guidelines.

ACM Templates

• Word (docx): Download

• LaTeX (zip): Download – use the manuscript format option (see sample/sample-manuscript.tex).

• Overleaf: Use the ACM template with the manuscript format option.

List of Topics

We invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. Topics of interest for this workshop include (but are not limited to):

• Example use-cases and case-studies that use RISC-V
• Lessons learnt from leveraging RISC-V in HPC
• Industry papers exploring the use of RISC-V
• The porting of codes to RISC-V
• Novel hardware and accelerators built upon RISC-V
• Tools and techniques to aid in the use of RISC-V for HPC
• Developments in HPC libraries to port them to RISC-V
• Enhancements to RISC-V to make the architecture more suited for HPC
• Compiler and runtime support for RISC-V
• The RISC-V ecosystem
• Future gazing how RISC-V might evolve the HPC community
• And anything else related to RISC-V and HPC!

Committees

Program Committee

        TBD

Organizing committee

• Nick Brown (EPCC at the University of Edinburgh)
• Enrique S. Quintana-Ortí (Universitat Politècnica de València)
• Sandra Catalán (Universitat Jaume I)

Publication

RISCV-HPC26 proceedings will be published together with SCA/HPCAsia proceedings.

Venue

The conference will be held in conjunction with SCA/HPCAsia 2026.

Contact

All questions about submissions should be emailed to catalans@uji.es, quintana@disca.upv.es and n.brown@epcc.ed.ac.uk