Industrial Temporal Logic Specifications for Falsification of Cyber-Physical Systems

8 pages•Published: September 25, 2020

Johan Lidén Eddeland, Alexandre Donzé, Sajed Miremadi and Knut Åkesson

Abstract

In this benchmark proposal, we present a set of large specifications stated in Signal Temporal Logic (STL) intended for use in falsification of Cyber-Physical Systems. The main purpose of the benchmark is for tools that monitor STL specifications to be able to test their performance on complex specifications that have structure similar to industrial specifications. The benchmark itself is a Git repository which will therefore be updated over time, and new specifications can be added. At the time of submission, the repository contains a total of seven Simulink requirement models, resulting in 17 generated STL specifications.

Keyphrases: cyber physical systems, falsification, signal temporal logic, specifications

In: Goran Frehse and Matthias Althoff (editors). ARCH20. 7th International Workshop on Applied Verification of Continuous and Hybrid Systems (ARCH20), vol 74, pages 267-274.

Links:	https://easychair.org/publications/paper/vfmh
	https://doi.org/10.29007/r74f

BibTeX entry

@inproceedings{ARCH20:Industrial_Temporal_Logic_Specifications,
  author    = {Johan Lidén Eddeland and Alexandre Donzé and Sajed Miremadi and Knut Åkesson},
  title     = {Industrial Temporal Logic Specifications for Falsification of Cyber-Physical Systems},
  booktitle = {ARCH20. 7th International Workshop on Applied Verification of Continuous and Hybrid Systems (ARCH20)},
  editor    = {Goran Frehse and Matthias Althoff},
  series    = {EPiC Series in Computing},
  volume    = {74},
  publisher = {EasyChair},
  bibsource = {EasyChair, https://easychair.org},
  issn      = {2398-7340},
  url       = {/publications/paper/vfmh},
  doi       = {10.29007/r74f},
  pages     = {267-274},
  year      = {2020}}

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