Solving Verification Challenges for Complex Devices with a Limited Number of Ports Using Debugports

EasyChair Preprint 15037

Abstract

With multi-fold increase in the complexity of modern IPs (Intellectual Property) and shrinking of the die sizes with the reduction of the technology nodes to sub 5 nanometer, number of pins/ports on the devices has become expensive with general direction of minimizing the number of device pin as much as possible. This introduces a challenge for verification engineers who mostly rely on the pinout signals and waveforms to debug subsystems and IPs for unexpected errors. This presentation talks about a unique and a generic way to expose internal device signals, logic variables and registers on the waveform to assist IP (Intellectual Property) and SoC (System on Chip) verification engineers for dramatic improvement in the debuggability and visibility of internal device signals, commands, and transaction without any change in the pinout of any of the devices.

Keyphrases: Functional Verification, SystemC, SystemVerilog, Verification IP, debugports, memory model

@booklet{EasyChair:15037,
  author    = {Shyam Sharma and Shravan Soppi},
  title     = {Solving Verification Challenges for Complex Devices with a Limited Number of Ports Using Debugports},
  howpublished = {EasyChair Preprint 15037},
  year      = {EasyChair, 2024}}