Power Optimization in High Performance Advanced Micro-Controller Bus Architecture in AHB

EasyChair Preprint 3447

Abstract

AHB which is Advanced High-performance Bus is a high-performance bus in AMBA (Advanced Microcontroller Bus Architecture) based Micro-controller. It is widely used as an interconnection standard for System on Chip (SoC) design. In this paper, we present the design of the AMBA AHB protocol with different modes of operation. The design of the AHB Protocol is developed comprising of the basic blocks such as Master, Slave, Decoder, and Arbiter. This High-performance Bus has a very high speed of data transfer capacity which consumes an enormous amount of power. The power consumption is based on the switching behavior of the clock net. In this work, a technique to reduce the clock net has been developed. All of these operations are developed in Verilog HDL. Modelsim (Simulation tool from Mentor Graphics) is used to simulate the design and X-Power Analyser (Graphical tool for power calculation from Xilinx) is used to calculate power and functional coverage.

Keyphrases: AMBA AHB, Gated Clock, Negative Latch, SoC, dynamic power

@booklet{EasyChair:3447,
  author    = {Abhishek Deshwal and Aman Singh and Ashutosh Gupta and Chiranjeev Singhal and P. C. Joshi},
  title     = {Power Optimization in High Performance Advanced Micro-Controller Bus Architecture in AHB},
  howpublished = {EasyChair Preprint 3447},
  year      = {EasyChair, 2020}}