Invited Paper: Opportunities of Chip Power Integrity and Performance Improvement Through Wafer Backside (BS) Connection

EasyChair Preprint 9239

Abstract

Technology node scaling leads to more chip system performance and power integrity bottleneck coming from back-end-of-line (BEOL). Power integrity degradation induced by on-chip (Power Delivery Network) PDN IR-drop results in increased power density and number of metal layers in BEOL and their resistivity. Meanwhile, signal routing limits the SoC performance improvements due to increased routing congestion and delays. To conquer these issues, we introduce a disruptive technology: wafter backside connection to realize chip BS PDN and BS signal routing. We first provide some key wafer processes features required and developed at imec to enable this technology. Further, we show benefits of this technology by demonstrating a large improvement in chip power integrity and performance after applying this technology to BSPDN and BS routing under a sub-3nm technology node design rule.

Keyphrases: BEOL, BS-signal Routing, BSPDN, IR-drop, SRAM macro, logic

@booklet{EasyChair:9239,
  author    = {Rongmei Chen and Giuliano Sisto and Odysseas Zografos and Dragomir Milojevic and Pieter Weckx and Geert Van der Plas and Eric Beyne},
  title     = {Invited Paper: Opportunities of Chip Power Integrity and Performance Improvement Through Wafer Backside (BS) Connection},
  howpublished = {EasyChair Preprint 9239},
  year      = {EasyChair, 2022}}